1. Field of the Invention
The present invention relates generally to the field of electrically programmable non-volatile memory devices. More particularly, the present invention relates to an SONOS (MONOS) type non-volatile memory array using induced (polysilicon bit line induced) bit lines.
2. Description of the Prior Art
Nitride-based non-volatile memories such as Nitride Read-Only-Memory (NROM), Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type or Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type non-volatile memory devices are known in the art. A nitride-based non-volatile memory cell is constructed having a non-conducting dielectric layer, typically a silicon nitride layer, sandwiched between two silicon dioxide layers. The non-conducting dielectric layer functions as an electrical charge-trapping medium. A conductive gate layer is placed over the upper silicon dioxide layer. Buried doping regions or buried bit lines are implanted into the substrate, which function as a buried drain or buried source for a selected memory cell depending on the desired operation conditions. Since the electrical charge is trapped and localized near whichever side that is used as the buried drain, this structure can be described as a two-transistor cell, or two-bit per cell (i.e., two physically separated storage areas per cell).
FIG. 1 schematically illustrates an enlarged cross-sectional view of a typical two-bit SONOS type memory cell 100. Generally, SONOS type memory cell 100 is programmed by injecting hot electron from a portion of the substrate 10, such as the channel section near the buried drain region, to the charge-trapping medium 24. Electron injection causes the accumulation of negative charge in the charge-trapping medium 24 that is sandwiched between the bottom oxide layer 22 and the top oxide layer 26. The injection mechanism can be induced by grounding the buried source region and a bulk portion of the substrate 10 and applying a relatively high positive voltage to the control electrode 30 to create an electron attracting field and applying a positive voltage of moderate magnitude to the buried drain region in order to generate hot electrons. After sufficient negative charge accumulates on the charge-trapping medium, the negative potential of the charge-trapping medium raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel region through a subsequent read mode. The magnitude of the read current is used to determine whether or not a SONOS type memory cell is programmed.
Conventionally, the buried bit lines 40 of the SONOS (MONOS) type memory are formed by implanting impurities into the substrate through a bit line mask prior to forming the ONO dielectric. Ordinarily, in order to reduce the buried bit line sheet resistance, a high-dosage ion implantation process is used. This is disadvantageous when the wafer is subjected to subsequent high temperature thermal cycles, because the doping impurities within the buried bit line regions tend to diffuse outwards, thereby laterally expanding the buried bit line regions towards one another, thus causing punch-through to take place between adjacent buried bit lines. From one aspect, the punch-through problem also hinders the cell shrinkage of such type of memories since adequate channel length has to be maintained.
To mitigate the excessive diffusion of the ion-implanted buried bit lines, Yang et al., in U.S. Pat. No. 6,436,768, teach a method of fabricating the source/drain regions of SONOS type non-volatile memory semiconductor devices. According to this patent, the source/drain implantation is carried out during ONO formation.